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21644-dsh-001-b mindspeed technologies ? july 2013 mindspeed proprietary and confidential features ? smpte 424m, smpte 292m, sm pte 344m, smpte 259m, and dvb-asi compliant ? robust adaptive cable equalization for up to 200 meters of belden 1694a at 2.97 gbps, up to 200 me ters of belden 1694a at 1.485 gbps, and up to 400 meters of belden 1694a at 270 mbps ? individually controllable dual diff erential output drivers with programmable 8 db of de-emphasis ? optional 6 db flat band gain at input ? cable length indication ? sd, hd and 3g data rate detection ? optional four-wire seri al digital interface ? very low power consumption: 105 mw (single output), 120 mw (dual output) ? power down and mute features ? extended operating temper ature range: -40 c to +85 c the m21644/54/64 are multi-rate, highly integrated, adaptive cable equalizers for sdi and dvb-asi video as well as digital audio applications. it provides adaptive, low noise, high gain equalization for 75 ? coaxial cable at sdi data rates from 125 mbps to 2.97 gbps. the device is capable of compensating for losses accumulated across cable length up to 200 m when operating at 2.97 gbps. the m21644/54 feature dual differential outputs, eliminating the need for additional circuitry and simplifying system design. b oth outputs feature programmable swing as well as de-emphasis for enabling the signal to be transmitted across 40" of fr4 trace. the second, optional output may be disabled for additional powe r savings. the m21664 offers a single output solution with a smaller footprint and maximum power savings. the device operates using a single 2.5 v supply voltage and has extremely low power consumption dissipating only 105 mw when one output driver is enabled. it may be used in either hardware mode, or controlled through a standard four-wire serial digital interface. furthermore, it features advanced diagnostic capabilities such as cable length indication, loss of signal detection, and offers power management functi ons such as power down upon loss of signal. the m21644/54/64 are offered in a green and ro hs compliant small footprint qfn package. functional block diagram de & prog. swing ctrl de & prog. swing ctrl digital interface adaptive eq prog. 6 db gain los mute sdi sdo0 sdo1 mux applications ? broadcast video routing and production switchers ? broadcast video di stribution amplifiers ? broadcast video ca meras and monitors m21644, m21654, m21664 3g/hd/sd-sdi long reach adaptive cable equalizer
21644-dsh-001-b mindspeed technologies ? 2 mindspeed proprietary and confidential ordering information part number package operating data rate operating temperature m21644g-13* 24-pin qfn (rohs compliant) 125?2970 mbps ?40 c to 85 c M21654G-13* 32-pin qfn (rohs compliant) 125?2970 mbps ?40 c to 85 c m21664g-13* 16-pin qfn (rohs compliant) 125?2970 mbps ?40 c to 85 c * the letter ?g? designator after the part number indicates a rohs-compliant package. refer to www.mindspeed.com for additional information. revision history revision level date description b release july 2013 updated electrical specifications. chapter 1.0 a advance april 2013 initial release. m21644/54/64 marking diagram 13 216x4 xxxx.x yyww xx part revision part number lot number date country code
21644-dsh-001-b mindspeed technologies ? 3 mindspeed proprietary and confidential 1.0 electrical characteristics table 1-1. absolute maximum ratings symbol parameter minimum maximum unit v cc analog power supply voltage -0.5 2.75 v v in,pcml dc input voltage (pcml) v ss - 0.5 av dd + 0.5 v v in,cmos dc input voltage (cmos) v ss - 0.6 dv dd + 0.5 v t store storage temperature -65 150 c t junc junction temperature ? 125 c v esd,hbm electrostatic discharge voltage (hbm) -3000 3000 v v esd,cdm electrostatic discharge voltage (cdm) -500 500 v v esd, mm electrostatic discharge voltage (mm) -150 150 v notes: 1. exposure of the device beyond the minimum/maximum limits may cause permanent damage. 2. hbm and cdm per jedec class 2 (jesd22-a114-b). 3. limits listed in the above table ar e stress limits only and do not imply func tional operation wi thin these limits. table 1-2. recommended operating conditions symbol parameter minimum typical maximum unit v cc analog power supply voltage 2.37 2.5 2.63 v t case operating case temperature -40 ? 85 c ? jc junction to case thermal resistance m21644/64 ? ? 13.8 c/w m21654 ? ? 11.5 c/w notes: 1. thermal resistance value is calculated using a 5% increase on the supply voltage and includ es all temperature variations. table 1-3. power consumption specifications (1 of 2) symbol parameter typical maximum unit i cc core current consumption one output enabled. intermediate swing 42 54 ma maximum swing 44 56 ma two outputs enabled intermediate swing 48 61 ma maximum swing 51 64 ma
electrical characteristics 21644-dsh-001-b mindspeed technologies ? 4 mindspeed proprietary and confidential p total one output enabled. intermediate swing 105 142 mw two outputs enabled. intermediate swing 120 160 mw notes: 1. maximum current and maximum power consumption numbers are calcu lated using a 5% increase on the supply voltage, and include a ll temperature and process variations. table 1-4. pcml input/output electrical characteristics symbol parameter note minimum typical maximum unit dr nrz data rate 125 ? 2970 mbps v in differential input swing 720 800 880 mv pp r in input termination resistance ? 2.3 ? ?? c in input capacitance ? 0.4 ? pf s 11 input return loss from 5 mhz to 1.5 ghz ? ? -15 db s 11 input return loss from 1.5 ghz to 3 ghz ? ? -10 db v out differential output swing 1 250 390 540 365 555 740 480 720 940 mv ppd v ocm output common mode voltage 1 0.8 ? 1.2 v t r /t f output rise/fall time (20% - 80%) 2 ? 90 130 ps de highest output de-emphasis setting 3 0 ? 8 db jitter performance t jit total jitter added at 2.97 gbps for the following belden 1694a cable length 0 - 100 m 4, 5 ? ? 0.23 ui 100 - 140 m 4, 5 ? ? 0.32 140 - 180 m 4, 5 ? ? 0.45 180 - 200 m 4, 5 ? 0.45 ? total jitter added at 1.485 gbps for the following belden 1694a cable length 0 - 200 m 4, 5 ? 0.2 0.4 ui total jitter added at 270 mbps for the following belden 1694a cable length 0 - 400 m 4, 5 ? ? 0.3 ui notes: 1. programmable with 200 mv increments. 2. measured using a clock pattern with 50% duty cycle and consisting of 10 consecuti ve identical di gits (10 cid) 3. programmable in 2 db steps. 4. measured according to smpte rp184 and smpte rp192. 5. measured to ber 1e-09 using prbs-10 te st pattern and default output swing table 1-3. power consumption specifications (2 of 2) symbol parameter typical maximum unit
electrical characteristics 21644-dsh-001-b mindspeed technologies ? 5 mindspeed proprietary and confidential table 1-5. control/interface logic input/output characteristics symbol parameter note minimum typical maximum unit v oh digital output logic high 1 0.85 x v cc v cc ?v v ol digital output logic low 2 ? 0 0.15 x v cc v v ih digital input logic high 0.75 x v cc ?v cc v v il digital input logic low 0 ? 0.25 x v cc v v if digital input logic float 0.35 x v cc ? 0.65 x v cc v notes: 1. i oh = -4 ma. 2. i ol = 4 ma.
21644-dsh-001-b mindspeed technologies ? 6 mindspeed proprietary and confidential 2.0 typical performance characteristics unless otherwise noted, typical performance applies for v cc = 2.5 v, 25 c ambient temperature, 800 mv pp differential input data swing, prbs 2 10 ? 1 data pattern at 2.97 gbps. figure 2-1. eye diagram @2.97 gbps, unequalized signal, after 150 m belden 1694a cable figure 2-2. eye diagram @2.97 gbps, equalized signal, after 150 m belden 1694a cable
21644-dsh-001-b mindspeed technologies ? 7 mindspeed proprietary and confidential 3.0 pinout diagram, pin descriptions, and package outline drawing 3.1 m21644 pinout figure 3-1. m21644 pinout diagram (bottom view of the package) 1 m21644 4x4 ? mm ? 24 \ pin ? qfn ground pad v ee v ee 2 3 4 v ee sdip sdin 5 6 v ee mode_sel 18 sdo1p 17 16 15 sdo1n v ee sdo0p 14 13 sdo0n xcs 7 sdo1_disable agc+ agc- mf0 muteref v ee 8 9 10 11 12 19 mf1 v cc mf2 mf3 v ee v cc 20 21 22 23 24
pinout diagram, pin descriptions, and package outline drawing 21644-dsh-001-b mindspeed technologies ? 8 mindspeed proprietary and confidential 3.2 m21644 pin description table 3-1. m21644 pin descriptions (1 of 2) pin name pin number(s) type description v ee 1,2,5,12,16,23, ground pad ground negative power supply (ground) v cc 20,24 power positive power supply (2.5 v) sdip/sdin 3,4 i, sdi serial data input sdo0p/sdo0n 15,14 o, lvds serial data output 0 sdo1p/sdo1n 18,17 o, lvds serial data output 1 mode_sel 6 i, lvcmos mode select 1: software mode enabled (4-wire digital interface) 0: hardware mode enabled internal pull down sdo1_disable 7 i, lvcmos sdo1 disable pin 1: sdo1 disable 0: sdo1 enable internal pull up agc+/- 8,9 i/o, analog equalizer loop filter capacitor (33 nf) mf0 10 i, tri-state lvcmos hardware mode (mode_sel =0) bypass 1: bypass entirely the equalizer 0: normal operation software mode (mode_sel =1) xsd: signal detect complement 1: no input signal is present or the cabl e length is above the muteref threshold 0: input signal is present and cable length is below the muteref threshold muteref 11 i, analog mute reference input. defines the cable length threshold at which xsd will be asserted. by connecting xsd to mute, it controls the maximum cable length after which the part will mute. this pin can be left floating or can be grounded for maximum equalization. xcs 13 i, lvcmos hardware mode (mode_sel =0) must be set low for normal operation. software mode (mode_sel =1) chip select complement, internal pullup. mf1 19 i, lvcmos hardware mode (mode_sel =0) automatic sleep control. sleep mode has precedence over mute and bypass. 1: automatic power down when no input is present 0: normal mode, the equalizer is always active software mode (mode_sel =1) 4-wire: signal out internal pull up
pinout diagram, pin descriptions, and package outline drawing 21644-dsh-001-b mindspeed technologies ? 9 mindspeed proprietary and confidential mf2 21 i, lvcmos hardware mode (mode_sel =0) output mute. mute has precedence over bypass. 1: outputs are muted 0: normal operation software mode (mode_sel =1) 4-wire: sclk internal pull down mf3 22 i, lvcmos hardware mode (mode_sel =0) xsd: signal detect 1: no input signal is present or the cabl e length is above the muteref threshold 0: input signal is present and cable length is below the muteref threshold software mode (mode_sel =1) 4-wire: signal in internal pull down table 3-1. m21644 pin descriptions (2 of 2) pin name pin number(s) type description
pinout diagram, pin descriptions, and package outline drawing 21644-dsh-001-b mindspeed technologies ? 10 mindspeed proprietary and confidential 3.3 m21644 package information the m21644 is packaged in a 4 mm footprint, 24-pin qfn. figure 3-2. m21644 packaging drawing
pinout diagram, pin descriptions, and package outline drawing 21644-dsh-001-b mindspeed technologies ? 11 mindspeed proprietary and confidential 3.4 m21654 pinout figure 3-3. m21654 pinout diagram (bottom view of the package) 3 m21654 5x5 ? mm ? 32 \ pin ? qfn ground pad v ee sdip 4 5 6 sdin nc nc 7 8 v ee mode_sel 22 sdo1n 21 20 19 nc sdo0p sdo0n 18 17 xcs nc 9 agc+ agc- mf0 nc nc muteref 10 11 12 13 14 27 v cc mf2 mf3 v cc nc nc 28 29 30 31 32 1 nc 2 v ee nc nc 15 16 25 nc v cc 26 24 mf1 23 sdo1p
pinout diagram, pin descriptions, and package outline drawing 21644-dsh-001-b mindspeed technologies ? 12 mindspeed proprietary and confidential 3.5 m21654 pin description table 3-2. m21654 pin descriptions (1 of 2) pin name pin number(s) type description v ee 2,7, ground pad ground negative power supply (ground) v cc 26,27,30 power positive power supply (2.5 v) sdip/sdin 3,4 i, sdi serial data input sdo0p/sdo0n 20,19 o, lvds serial data output 0 sdo1p/sdo1n 23,22 o, lvds serial data output 1 mode_sel 8 i, lvcmos mode select 1: software mode enabled (4-wire digital interface) 0: hardware mode enabled internal pull down agc+/- 9,10 i/o, analog equalizer loop filter capacitor (33 nf) mf0 11 i, tri-state lvcmos hardware mode (mode_sel =0) bypass 1: bypass entirely the equalizer 0: normal operation software mode (mode_sel =1) xsd: signal detect complement 1: no input signal is present or the cable length is above the muteref threshold 0: input signal is present and cable length is below the muteref threshold muteref 14 i, analog mute reference input. defines the cab le length threshold at which xsd will be asserted. by connecting xsd to mute, it controls the maximum cable length after which the part will mute. this pin can be left floating or can be grounded for maximum equalization. xcs 18 i, lvcmos hardware mode (mode_sel =0) must be set low for normal operation. software mode (mode_sel =1) chip select complement, internal pullup. mf1 24 i, lvcmos hardware mode (mode_sel =0) automatic sleep control. sleep mode has precedence over mute and bypass. 1: automatic power down when no input is present 0: normal mode, the equalizer is always active software mode (mode_sel =1) 4-wire: signal out internal pull up
pinout diagram, pin descriptions, and package outline drawing 21644-dsh-001-b mindspeed technologies ? 13 mindspeed proprietary and confidential mf2 28 i, lvcmos hardware mode (mode_sel =0) output mute. mute has precedence over bypass. 1: outputs are muted 0: normal operation software mode (mode_sel =1) 4-wire: sclk internal pull down mf3 29 i, lvcmos hardware mode (mode_sel =0) xsd: signal detect 1: no input signal is present or the cable length is above the muteref threshold 0: input signal is present and cable length is below the muteref threshold software mode (mode_sel =1) 4-wire: signal in internal pull down nc 1,5,6,12,13, 15,16,17,21, 25,31,32 no connect table 3-2. m21654 pin descriptions (2 of 2) pin name pin number(s) type description
pinout diagram, pin descriptions, and package outline drawing 21644-dsh-001-b mindspeed technologies ? 14 mindspeed proprietary and confidential 3.6 m21654 package information the m21654 is packaged in a 5 mm footprint, 32-pin qfn. figure 3-4. m21654 packaging drawing
pinout diagram, pin descriptions, and package outline drawing 21644-dsh-001-b mindspeed technologies ? 15 mindspeed proprietary and confidential 3.7 m21664 pinout figure 3-5. m21664 pinout diagram (bottom view of the package) 5 6 7 8 16 15 14 13 1 m21664 4x4 ? mm ? 16 \ pin ? qfn ground pad v ee v ee 2 3 4 12 11 10 9 sdip sdin mf1 sdop sdon xcs mode_sel agc+ agc- mf0 muteref v cc mf3 mf2 v cc
pinout diagram, pin descriptions, and package outline drawing 21644-dsh-001-b mindspeed technologies ? 16 mindspeed proprietary and confidential 3.8 m21664 pin description table 3-3. m21664 pin descriptions (1 of 2) pin name pin number(s) type description v ee 1, ground pad ground negative power supply (ground) v cc 13,16 power positive power supply (2.5 v) sdip/sdin 2,3 i, sdi serial data input sdop/sdon 11,10 o, lvds serial data output 0 mode_sel 4 i, lvcmos mode select 1: software mode enabled (4-wire digital interface) 0: hardware mode enabled internal pull down agc+/- 5,6 i/o, analog equalizer loop filter capacitor (33 nf) mf0 7 i, tri-state lvcmos hardware mode (mode_sel =0) bypass 1: bypass entirely the equalizer 0: normal operation software mode (mode_sel =1) signal detect 1: no input signal is present or the cable length is above the muteref threshold 0: input signal is present and cable le ngth is below the muteref threshold muteref 8 i, analog mute reference input. defines the cable length threshold at which xsd will be asserted. by connecting xsd to mute, it cont rols the maximum cable length after which the part will mute. this pin can be left floating or can be grounded for maximum equalization. xcs 9 i, lvcmos hardware mode (mode_sel =0) must be set low for normal operation. software mode (mode_sel =1) chip select complement, internal pullup. mf1 12 i, lvcmos hardware mode (mode_sel =0) automatic sleep control. sleep mode has precedence over mute and bypass. 1: automatic power down when no input is present 0: normal mode, the equalizer is always active software mode (mode_sel =1) 4-wire: signal out internal pull up
pinout diagram, pin descriptions, and package outline drawing 21644-dsh-001-b mindspeed technologies ? 17 mindspeed proprietary and confidential mf2 14 i, lvcmos hardware mode (mode_sel =0) output mute. mute has precedence over bypass. 1: outputs are muted 0: normal operation software mode (mode_sel =1) 4-wire: sclk internal pull down mf3 15 i, lvcmos hardware mode (mode_sel =0) xsd: signal detect 1: no input signal is present or the cable length is above the muteref threshold 0: input signal is present and cable le ngth is below the muteref threshold software mode (mode_sel =1) 4-wire: signal in internal pull down table 3-3. m21664 pin descriptions (2 of 2) pin name pin number(s) type description
pinout diagram, pin descriptions, and package outline drawing 21644-dsh-001-b mindspeed technologies ? 18 mindspeed proprietary and confidential 3.9 m21664 package information the m21664 is packaged in a 4 mm footprint, 16-pin qfn. figure 3-6. m21664 packaging drawing
21644-dsh-001-b mindspeed technologies ? 19 mindspeed proprietary and confidential 4.0 functional descriptions the m21644/54/64 devices are part of the next generation cable equalizer family for sdi video applications. they allow the transmission of data over of 200 m belden 1694a cable at 3 gbps, 200 m at 1.5 gbps and 400 m at 270 mbps. the equalizer has an integrated automatic rate detect (ard) circuitry that allows the detection of an sd or hd/3g data rates. the m21644 and m21654 provide two serial data outputs where as the m21664 provides one serial data ouput, all outputs have very low alignment jitter. the m21644/54/64 support limited configuration through hardware pin settings (hardware mode) or for additional configuration settings, a digital interface is also available (software mode). the mode is selected via pin. mode_sel figure 4-1. m21644/54 block diagram sdo0[p/n] digital interface (hardware or 4-wire mode acess) mode_sel sdo1_disable sdip output buffer 1 programmable output swing , vcm and de -em phasis drv input buffer adaptive equalization , 6 db attenuation and signal detection adaptive eq output buffer 0 programmable output swing , vcm and de -em phasis drv mf0 mf1 mute muteref xcs mf2 mf3 5.6nh 1uf 37.5 ? sdin 1uf 75 ? 75 ? bnc sdo1[p/n] m21644/54 v cm v cm bypass
functional descriptions 21644-dsh-001-b mindspeed technologies ? 20 mindspeed proprietary and confidential 4.1 high-speed input digital video coaxial cables are ac-coupled to the high-speed low-noise inputs ( sdip/sdin ). these are designed to operate in both single-ended or differential mode. the typical application is single-ended into the non-inverting sdi input with the inverting sdi input biased to match the bias on the input used. the m21644/54/64 do not contain any internal input terminations and require both external input termination as well as the matching circuit to exceed the smpte input re turn loss specifications. the package and ic design have been optimized for high-speed performance, allowing them to exceed the sd/hd/3g smpte return loss. for non-inverting single-ended operation, the recommended input circuit is shown in figure 4-1 . for differential operation, the matching/termination circuit on sdip should be duplicated on sdin . 4.1.1 input signal detection the high-speed input block offers a signal detect function that can be monitored either with pin. mf3 or register. genconfig bit[7]. the signal detect is also used to turn off the device if there is no signal present at the input. if desired, this function can be bypassed using register. genconfig bit[4:3] or by setting pin. mf1 = low in hardware mode. figure 4-2. m21664 block diagram sdo0[p/n] digital interface (hardware or 4-wire mode acess) mode_sel sdip input buffer adaptive equalization , 6db attenuation and signal detection adaptive eq output buffer 0 programm able output swing , vcm and de -em phasis drv v cm mf0 mf1 mute muteref xcs mf2 mf3 5.6nh 1uf 37.5 ? sdin 1uf 75 ? 75 ? bnc bypass m21664
functional descriptions 21644-dsh-001-b mindspeed technologies ? 21 mindspeed proprietary and confidential 4.1.2 adaptive equalizer in typical hardware mode operation, the adaptive equalization is enabled with pin. mf0 = low (bypass disabled). however, with pin. mf0 = high, the adaptive equalization and dc restore circuit are bypassed and the input is fed directly to the output buffers. in software mode operation, the equalizer block can be bypassed by setting register. genconfig .bit[5] to 1b. the adaptive equalizer can be set to have a 6 db gain for applications that have 400 mv pp launch amplitude instead of 800 mv pp . to have this 6 db gain, register 00h bit[2] ( register.launch_ctrl ) must be set to 1b. once there is a signal detect ed at the input of the equal izer, the adaptive equalizer has the ability to report what length of belden 1694a cable is being used. the cable length indicator results can be read on registers 05h bit[0] and register 06h bit[7:0]. the formulas to calculate the estimated cable length are: cl(m) = 0.625*cli, for 0-250 m cl(m) = 2.5*(cli - 400) + 250, for >250 m where cli is the decimal value of the 9 bits from registers 05h bit[0] (msb) and register 06h bit[7:0] (lsb) and cl is the estimated belden 1694a cable length in meters. ta b l e 4 - 1 has some of the decoded values for the cable length indicator registers. table 4-1. cable length indicator decoder cli results estimated cable length* 000000000 0 m 000101000 25 m 001010000 50 m 001111000 75 m 010100000 100 m 011001000 125 m 011110000 150 m 100011000 175 m 101000000 200 m 101101000 225 m 110010000 250 m 110100100 300 m 110111000 350 m 111001100 400 m 111100000 450 m * all cable length indicator values are approximate and are not guaranteed.
functional descriptions 21644-dsh-001-b mindspeed technologies ? 22 mindspeed proprietary and confidential 4.1.3 6 db attenuation the m21644/54/64 provide an option to compensate for 6 db of flat attenuation in applications where the launch amplitude is a lot lower than 800 mv ppd . when the expected launch amplitude is between ~300 mv ppd and ~500 mv ppd , setting register. genconfig ,bit[2] to 1b will improve the equalizer?s performance specially for sd rates. 4.2 high-speed outputs the high-speed lvds differential outputs after equalization are made available on the pin. sdo0[p/n] and pin. sdo1[p/n] pins. note that the m21664 has only one output available, pin. sdo0[p/n] . there are three output swings available - 400 mv pp , 600 mv pp (default) and 800 mv pp . the output swing levels can only be controlled via register. outputdriver [1:0].bit[7:6]. in addition to controlling the output swing, the common mode voltage (v cm ), can also be modified to auto mode for low common mode dc impedance, 0.8 v, 1.0 v or 1.2 v(default) by programming the desired value to register. outputdriver [1:0].bit[5:4]. when the output dr iver is set to have automati c common mode voltage, it will sense the downstream device input common mode and it will match it. no te, the maximum co mmon mode voltage is 1.2 v. in order to improve signal integrity when used in large systems, each output also comes equipped with programmable de-emphasis (de) for fr4 traces. there are four settings for output de-emphasis: 0 db (or no de), 2 db, 4 db, and 6 db. in software mode, the output de-emphasis level for each input may be set by programming the desired value to register. outputdriver [1:0].bit[3:1]. 4.3 control modes the m21644/54/64 may be configured in two separate control modes. the control mode is determined by the setting of the pin. mode_sel pin as shown in ta b l e 4 - 2 below. table 4-2. control mode setting mode_sel control mode pin. mode_sel = l hardware mode pin. mode_sel = h software mode (4-wire digital interface)
functional descriptions 21644-dsh-001-b mindspeed technologies ? 23 mindspeed proprietary and confidential 4.3.1 hardware mode configuring the m21644/54/64 in hardware mode avoids the complication of adding a microcontroller, but offers limited control options. when in hardware mode, the mf (multi function io) pins are configured as shown in ta bl e 4 - 3 below. 4.3.2 software mode (4-wire digital interface access) in this mode, a four-wire serial interface is used to program the device's internal registers, configuring the operation of the m21644/54/64. when in software mode, mf[3:0] pins comprise the four-wire bus as well as additional diagnostics as shown in ta b l e 4 - 4 below. 4.4 digital interface the 4-wire serial interface is selected with pin. mode_sel =h. the interface shifts data in from the external controller on the rising edge of the serial clock ( sclk ). the serial i/o operation is gated by chip select ( xcs ). data is shifted to the m21644/54/64 from the host (master) on the serial input ( si ) on the falling edge of sclk , and shifted out through the serial output ( so ) on the rising edge of sclk . to address a register, a 10-bit input needs to be shifted using si , consisting of the start bit (sb) = 1, the operation bit (op) = 1 for read, = 0 for write; and the 8-bit address (msb first). table 4-3. mf pin configuration in hardware mode (mode_sel = 0) pin name hardware mode pin name function pin. mf0 bypass eq bypass* pin. mf1 autosleep power down eq when no input signal is present pin. mf2 mute output mute pin. mf3 xsd signal detect (active low) * please see pin descriptions for more details. table 4-4. mf pin configuration in software mode (4-wire interface mode, mode_sel = 1) pin name 4-wire mode pin name function pin. mf0 xsd signal detect (active low) pin. mf1 s0 serial data output pin. mf2 sck serial data clock pin. mf3 si serial data input pin. xcs xcs chip select (active low)
functional descriptions 21644-dsh-001-b mindspeed technologies ? 24 mindspeed proprietary and confidential figure 4-4 illustrates the serial write mode . to initiate a write sequence, xcs goes low before the falling edge of sclk. on each falling edge of the clock, the 18 bits consisting of t he start bit = 1, op = 0 for write, addr (8-bit), and data (8-bit), are latched into the input shift register through ? si. ? the rising edge of xcs must occur before the falling edge of sclk for the last bit. upon receipt of the last bit, one additional cycle of sclk is necessary before data transfers from the input shift register to the addressed register. figure 4-6 illustrates the serial read mode to initiate a read sequence. xcs goes low before the falling edge of sclk. on each falling edge of sclk , the 10 bits consisting of start bit = 1, op = 1 for read, and the 8-bit addr are written to the serial input shift register and copied to the serial output shift register. on the next rising edge after the address lsb, the sb and 8 bits of the data are shifted out. the 4-wire serial interface supports multiple consecutive writes and reads, see figure 4-5 and figure 4-7 respectively. in these cases, the addr ess header is not nee ded and each additional 8 bits of data will be written into consecutive addresses. if consecutive read/write cycles are being performed, it is not necessary to insert an extra clock cycle between read/write cycles, however one extra clock cycle is needed after the last data bit of the last read/write cycle. notes: on a write cycle, any bits that follow the expected nu mber of bits will be ignored. on a read cycle, any extra clock cycles will result in the repeat of the data lsb. an invalid sb or op renders the operation undefined. the falling edge of ? xcs ? always resets the serial operation for a new read or write cycle. figure 4-3. 4-wire serial digital interface figure 4-4. 4-wire random write timing diagram sclk xcs 1 si so 2 3 ... 10 11 12 13 19 20 address[7:0] data[7:0] 0 t cs t dh t ds 1 14 15 16 17 18 21 t dh t cs t ch sb op
functional descriptions 21644-dsh-001-b mindspeed technologies ? 25 mindspeed proprietary and confidential figure 4-5. 4-wire sequential write timing diagram figure 4-6. 4-wire random read timing diagram figure 4-7. 4-wire sequential read timing diagram sclk xcs 1 si so 2 3 ... 10111213 ... 18 19 address[7:0] 1 st data[7:0] 0 20 21 ... 26 27 2 nd data[7:0] 3 rd data[7:0] t cs t dh t ds 1 ... sb op sclk xcs 1 si so 2 3 ... 10 11 12 13 19 20 address[7:0] t cs t dh 1 14 15 16 17 18 21 1 sb op d7 d6 d5 d4 d1 d0 d3 d2 t dd sclk xcs 1 si so 2 3 ... 10 11 12 13 22 ... address[7:0] t cs t dh 1 14 ... 19 20 21 26 1 sb op t dd 1 st data[7:0] 2 nd data[7:0] 3 rd 27
functional descriptions 21644-dsh-001-b mindspeed technologies ? 26 mindspeed proprietary and confidential table 4-5. 4-wire serial interface specifications timing symbol description min typ max unit tds data set-up time 2 ? ? ns tdh data hold time 2.5 ? ? ns tcs xcs set-up time 2 ? ? ns tch xcs hold time 2.5 ? ? ns tdd read data output delay (for max load capacitor 30 pf and dv ddo @3.3 v) 2?16ns t freqw write 4-wire clock frequency ? ? 100 mhz t freqr read 4-wire clock frequency ? ? 25 mhz t dcd sclk pulse width 45 ? 55 %
21644-dsh-001-b mindspeed technologies ? 27 mindspeed proprietary and confidential 5.0 control register descriptions 5.1 address register description address: 00h register name: genconfig default value: 08'h description: general configuration register table 5-1. register summary address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default r/w 00h genconfig signal_detect mute bypass sleep mode lanch_ ctrl master _rst acq_rst 08'h r/w 01h outputdriver0 output_swing0 offset _voltage0 de_emphasis0 reserved b0'h r/w 02h outputdriver1 output_swing1 offset _voltage1 de_emphasis1 reserved b0'h r/w 03h muteref muteref_mode digital_muteref reserved 7c'h r/w 04h misc rate_indicator reserved die_rev 80'h r 05h cablelengthindic ator1 reserved cable_leng ht_ind_bit 8 na r 06h cablelengthindic ator0 cable_length_ind_bit7 na r bit(s) name description default type 7 signal_detect 0b: no signal detected 1b: signal detected r 6 mute 0b: normal operation 1b: equalizer muted 0b r/w 5 bypass 0b: normal operation 1b: equalizer bypassed 0b r/w [4:3] sleep_mode 00b: forced enable of the equalizer 01b: power down when no input signal detected 10b: forced power down of the equalizer 11b: reserved 01b r/w
control register descriptions 21644-dsh-001-b mindspeed technologies ? 28 mindspeed proprietary and confidential address: 01h register name: outputdriver0 default value: b0'h description: output driver 0 configuration register 2 launch_ctrl 0b: equalizer expects 800 mv launch 1b: equalizer expects 400 mv (6 db attenuation) 0b r/w 1 master_rst 0b: no reset 1b: reset of registers and state machine (self clearing) 0b r/w 0 acq_rst 0b: no reset 1b: reset state machin e only (self clearing) 0b r/w bit(s) name description default type [7:6] output_swing 00b: power down of driver 0 01b: 400 mv differential peak to peak swing 10b: 600 mv differential peak to peak swing 11b: 800 mv differential peak to peak swing 10b r/w [5:4] offset_voltage 00b: auto mode to drive a r eceiver presenting a low common mode dc impedance 01b: 0.8 v output common mode 10b: 1 v output common mode 11b: 1.2 v output common mode 11b r/w [3:1] de_emphasis 000b: de-emphasis disable 001b: 2 db de-emphasis 011b: 4 db de-emphasis 101b: 6 db de-emphasis 111b: 8 db de-emphasis 000b r/w 0 rsvd reserved (set to default) 0b r/w bit(s) name description default type
control register descriptions 21644-dsh-001-b mindspeed technologies ? 29 mindspeed proprietary and confidential address: 02h register name: outputdriver1 default value: b0'h description: output driver1 configuration register address: 03h register name: muteref default value: 7c'h description: muteref configuration register bit(s) name description default type [7:6] output_swing 00b: power down of driver 1 01b: 400 mv differential peak to peak swing 10b: 600 mv differential peak to peak swing 11b: 800 mv differential peak to peak swing 10b r/w [5:4] offset_voltage 00b: auto mode to drive a r eceiver presenting a low common mode dc impedance 01b: 0.8 v output common mode 10b: 1 v output common mode 11b: 1.2 v output common mode 11b r/w [3:1] de_emphasis 000b: de-emphasis disable 001b: 2 db de-emphasis 011b: 4 db de-emphasis 101b: 6 db de-emphasis 111b: 8 db de-emphasis 000b r/w 0 rsvd reserved (set to default) 0b r/w bit(s) name description default type 7 muteref_mode 0b: analog mutere f with external pin voltage 1b: digital muteref 0b r/w [6:2] digital_muteref 0 0000b: mute when cable > 10 m 0 0010b: mute when cable > 25 m ... 0 1010b: mute when cable > 100 m 0 1100b: mute when cable > 125 m 0 1111b: mute when cable > 150 m 1 0001b: mute when cable > 175 m 1 0100b: mute when cable > 200 m ? 1 1001b: mute when cable > 250 m 1 1010b: mute when cable > 300 m 1 1011b: mute when cable > 350 m 1 1100b: mute when cable > 400 m 1 1110b: mute when cable > 450 m 1 1111b: never mute 1 1111b r/w [1:0] reserved reserved (set to default) 00b r/w
control register descriptions 21644-dsh-001-b mindspeed technologies ? 30 mindspeed proprietary and confidential address: 04h register name: misc default value: 00'h description: miscellaneous register address: 05h register name: cablelengthindicator1 default value: na description: adaptation results of equalizer address: 06h register name: cablelengthindicator0 default value: na description: adaptation results of equalizer bit(s) name description default type [7:6] rate_indicator 00b: sd rate 01b: unused 10b: unused 11b: hd rates (1.5 gbps or 3 gbps) 00b r [5:4] rsvd reserved 00b r/w [3:0] die_rev 0000b: die revision 0001b r bit(s) name description default type [7:1] rsvd reserved (set to default) 0b r 0 cable_lenght_ind_bit8 cable_length_ind[8]. bit 8 of the cable length indication na r bit(s) name description default type [7:0] cable_lenght_ind_bit[7:0] cable_length[7:0]. bits [7:0] of the cable length indication na r notes: 1. a numerical value of 0 corresponds to the shortest cable. the maximum value allowed for the cable length indicator is 1011110 11.
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